基于比较器抖动的数字后台校准算法

A digital backstage calibration using comparator dithering

提出一种应用于14bit100MS/s流水线模数转换器(ADC)的数字后台校准算法.该算法利用伪随机信号(PN)随机改变子ADC中比较器的阈值电压,间接注入宽度大幅度抖动信号测量ADC电路中由于电容失配和放大器有限增益造成的误差,并在数字域内对这些误差进行补偿.该方法能有效减小因电容失配和放大器有限增益等非理想因素对流水线ADC性能的影响,改善ADC的动态性能.该算法实现过程中无须增加采样电容和比较器数目,校准运算时无须复杂计算,实现简单,应用灵活.仿真结果表明:采用该技术校准后,流水线ADC的信号噪声失真比从63.3dB提高到78.7dB,无杂散动态范围从65.5dB提高到93.3dB.

A digital backstage calibration technique for a 14 bit 100 MS/s pipelined ADC （analog-to-digital converter） was proposed, which changed the threshold levels of sub analog-to-digital converters （ADCs） according to a pseudo-random noise （PN） pulse sequence. A large magnitude wideband dithers were injected into the ADC and measures the nonlinearity errors resulting from finite gain and capacitor mismatch in multiplying digital-to-analog converter （MDAC） were measured, which were fed back to the digital outputs of pipelined ADC for correction. This calibration method can efficiently suppress the impact caused by the capacitor mismatch and finite opamp gain errors without adding extra number of sampling capacitors and comparators, and is easy to realize without complex mathematic operation. Simulation results show that using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 63.3 dB to 78.7 dB and the spurious-free dynamic range （SFDR） improves from 65.5 dB to 93.3 dB.