期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

基于频域特性的流水线ADC数字校正技术 被引量：1

A calibration technique based on frequency-domain characteristics for pipelined ADCs
下载PDF
导出
摘要 针对流水线结构模拟数字转换器(ADC)中电容失配及放大器增益非线性引入的误差,提出一种新的数字校正技术.基于误差的频域特性,对电容失配和放大器增益非线性进行检测.每次检测后,通过变步长爬山算法和迭代算法,在数字域相应地调整校正函数来消除误差.基于该数字校正方法设计一个带有放大器增益非线性和1%电容失配的15位100MSPS的流水线ADC.仿真结果表明,经过数字校正SNDR和SFDR分别从56.4dB和60.4dB提高到91dB和107.6dBc,验证了该数字校正方法的有效性. This paper proposed a novel digital calibration technique that can correct the capacitor mismatch and amplifier gain nonlinearity errors in pipelined ADCs.These errors were estimated based on their frequency-domain characteristics.Every time after estimation,the recovery function in digital domain was adjusted accordingly through a variable-step hill-climbing algorithm and an iteration algorithm to cancel those errors.Based on the proposed calibration method,a 15-bit 100MSPS pipelined ADC with amplifier gain nonlinearity and 1% capacitor mismatch was designed.Simulation results show that SNDR and SFDR improve from 56.4 dB to 91 dB and from 60.4 dBc to 107.6 dBc with this calibration technique,respectively.The effectiveness of the proposed calibration method is verified.
作者 孙可旭 何乐年
机构地区 浙江大学超大规模集成电路设计所
出处 《浙江大学学报（工学版）》 EI CAS CSCD 北大核心 2013年第8期1393-1402,共10页 Journal of Zhejiang University：Engineering Science
关键词 数字校正 流水线模数转换器 高阶非线性误差 digital calibration pipelined ADC high-order nonlinearity errors
分类号 TN401 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献14

  • 1IIZUKA K, MATSUI H, UEDA M, et al. A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40MS/s [J. IEEE Journal of Solid-State Circuits, 2006, 41 ( 4 ) .- 883 - 890.
  • 2MING J, LEWIS S H. An 8-bit 80Msample/s pipelined analog-to-digital converter with background calibration [J. IEEE Journal of Solid-State Circuits, 2001, 36 (10) . 1489 - 1497.
  • 3SHU Y S, SONG B S. A 15-bit linear 20-MS/s pipe- lined ADC digitally calibrated with signal-dependent dithering [J]. IEEE Journal of Solid-State Circuits, 2008, 43(2): 342-350.
  • 4MASSOLINI R G, CESURA G, CASTELLO R. A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC [J]. IEEE Trans. Circuits Syst. II, Express Briefs, 2006, 53(5) .- 389 - 393.
  • 5SUN K, HE L. Parallel background calibration with signal-shifted correlation for pipelined ADC [C]// IEEE 13th International Symposium on Integrated Circuits. Singapore: IEEE, 2011, 11: 340-343.
  • 6孙可旭,何乐年.A fast combination calibration of foreground and background for pipelined ADCs[J].Journal of Semiconductors,2012,33(6):84-94. 被引量：1
  • 7MURMANN B, BOSER B. A 12-bit 75-MS/s pipelined ADC using opewloop residue amplification [J]. IEEE Journal of Solid-State Circuits, 2003, 38 ( 12 ) : 2040 - 2050.
  • 8MURMANN B. Digital calibration for low-power high- performance A/D conversion [D]. Berkeley: University of California Berkeley, 2003.
  • 9PENGB, LI H, LEESC, LINP F , et al. A virtual- ADC digital background calibration technique for multi- stage A/D conversion [J]. IEEE Trans. Circuits Syst.II, Express Briefs, 2010, 57(11). 853-857.
  • 10PENGB, HUANGGZ, LI H, et al. A48-mW, 12- bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS [C// IEEE Custom Integrated Circuits Conference (CICC). San Jose: IEEE, 2011: 1- 4.

二级参考文献23

  • 1Iizuka K, Matsui H, Ueda M, et al. A 14-bit digitally self- cali- brated pipelined ADC with adaptive bias optimization for arbi- trary speeds up to 40 MS/s. IEEE J Solid-State Circuits, 2006, 41:883.
  • 2Shu Y S, Song B S. A 15-bit linear 20-MS/s pipelined ADC dig- itally calibrated with signal-dependent dithering. IEEE J Solid- State Circuits, 2008, 43:342.
  • 3Ming J, Lewis S H. An 8-bit 80-Msample/s pipelined analog-to- digital converter with background calibration. IEEE J Solid-State Circuits, 2001, 36(10): 1489.
  • 4Liu H C, Lee Z M, Wu J T. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE J Solid-State Circuits, 2005, 40(5): 1047.
  • 5Fan J L, Wang C Y, Wu J T. A robust and fast digital background calibration technique for pipelined ADCs. IEEE Trans Circuits Syst I, Reg Papers, 2007, 54(6): 1213.
  • 6Ahmed I,Johns D A. An ll-bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage. IEEE J Solid-State Circuits, 2008, 43(7): 1626.
  • 7Massolini R G, Cesura G, Castello R. A fully digital fast conver- gence algorithm for nonlinearity correction in multistage ADC. IEEE Trans Circuits Syst II, Express Briefs, 2006, 53(5): 389.
  • 8Galton I. Digital cancellation of D/A converter noise in pipelined A/D converters. IEEE Trans Circuits Syst II, Analog Digit. Signal Process, 2000, 47(3): 185.
  • 9Li J, Moon U K. Background calibration techniques for multi- stage pipelined ADCs with digital redundancy. IEEE Trans Cir- cuits Syst II, Analog Digit Signal Process, 2003, 50(9): 531.
  • 10Siragusa E, Galton I. A digitally enhanced 1.8-V 15-bit 40- MSample/s CMOS pipelined ADC. IEEE J Solid-State Circuits, 2004, 39(12): 2126.

同被引文献6

  • 1Lan D, Liu X D. Behavioral model based on simulink for 14-bit 200MS/s pipelined ADC[C]// InternationalConference on Control Engineering and Communi- cat- ion Technology. Shenyang. IEEE, 2012. 79-82.
  • 2IEEE-SA Standards Board. IEEE Std 1076. 1-1999. Definition of analog and mixed signal extensions to IEEE Standard VHDL[S]. New York: The Institute of Electrical and Electronics Engineers, Inc, 1999.
  • 3AMS Modeling Cookbook for VHI)L-AMS. Mentor Graphics Corporation [ R]. MentorGraphics Corpora- tion, 2010.
  • 4Mikael G, J Jacob Wikner, Tan N X N. CMOS data converters for communications[M]. Boston: Kluwer Academic Publishers, 2000.
  • 5Xu D J, Jun P. The study of code density histogram testing method to high-speed ADC based on DSP[C]// Proc of the 8th World Congress on Intellgent Control and Automation. Jinan: IEEE, 2010: 2069-2074.
  • 6刘蒲霞,陆铁军,王宗民.16位流水线ADC系统级建模及仿真[J].微电子学与计算机,2009,26(12):120-124. 被引量：5

引证文献1

二级引证文献1

浙江大学学报（工学版）
2013年 第8期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部