一种运算簇间互连通信单元的设计

A Design of Arithmetic Cluster Inter Communication Unit

在高性能并行处理器设计中,权衡通信效率与硬件设计开销是一个关键的问题。基于此,在基于簇状处理单元的线性阵列处理器架构前提下,提出一种基于多运算簇处理器结构的运算簇间互连通信设计方案,包括通信单元结构和典型数字信号处理数据传输的应用案例分析。实验结果表明,与传统线性阵列处理器结构相比,该方案可使互连通信单元的相应性能提升30%以上。

How to balance the inter communication efficiency and the hardware cost is a key concern for most design of high performance processor. In order to solve this problem, this paper proposes a novel design of arithmetic cluster inter communication structure based on a processor architecture, Multiple Cluster Processor（MCP）, on the premise of cluster processing unit of the linear array processor architecture. It mainly includes communication unit structure and the analysis for the communication performance with some typical DSP application. Experimental results show that the design can increase the communication performance about 30% than the other tranditional linear array processor architectures.