摘要
An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18/zm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mme. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is -48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.
An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18/zm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mme. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is -48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.
基金
supported by the PhD Programs Foundation of Ministry of Education of China(No.2009009211001)
the Important National Science&Technology Specific Projects(No.2010ZX03006-003-02)
