MIMO-OFDM系统二相ACS前向回溯基4 Viterbi译码器设计与实现

Design and Implementation of Two-Phase ACS and Pre-Traceback Radix-4 Viterbi Decoder for MIMO-OFDM System

针对WLAN MIMO-OFDM系统在吞吐率、功耗、延时及硬件开销方面要求,该文提出了一种二相加比选(ACS)前向回溯基4 Viterbi译码器。利用基4算法分支输出反对称特性,该译码器按网格图状态进行ACS二相处理,既可保证MIMO-OFDM系统高吞吐率要求,也能减少近一半ACS运算单元开销。同时译码器采用前向回溯法,在维持功耗低特性基础上,进一步减少译码延时。在WLAN 2×2 MI MO-OFDM系统平台中进行前仿和后仿,测试结果验证了该译码器在1/2、2/3、3/4及5/6码率时的功能和性能,满足系统高吞吐率要求,与全并行ACS单元相比,此二相ACS可节省40%运算资源,与传统回溯算法相比,译码器延时可减小25%。

A two-phase ACS and pre-traceback Viterbi Decoder based on radix-4 algorithm is proposed for IEEE WLAN MIMO-OFDM system. Using the anti-symmetric branch output of radix-4 algorithm, a two-phase ACS architecture is proposed which can satisfy the requirement of high throughout of MIMO- OFDM system and reduce the resource of ACS by about a half. Meanwhile, the pre-traceback architecture is adopted by the survivor path memory unit, maintaining the characteristic of low-power and reducing the latency of decoder. Under the bench of WLAN 2x2 MIMO-OFDM system, the testing results validate the function and performance of the decoder in the configuration of 1/2,2/3,3/4 and 5/6, and it can satisfy the requirement of high throughout and latency. Compared to full parallel ACS, the two- phase ACS architecture achieves up to about 40% resource saving; Compared to conventional traceback architecture, the decoding latency is reduced by as much as 25%.