带自测功能的DDR2控制器设计

Design a controller of DDR2 with self-test function

在研究了JEDEC制定的DDR2标准的基础上,基于对DDR2快速测试的目的,设计了一种带自测功能的新型DDR2控制器。该控制器既拥有常见的控制时序、刷新、初始化等功能,又可以在没有外部激励的情况下对DDR2进行测试。整个设计完全遵循JEDEC标准,采用自顶向下的设计方法,通过异步FIFO进行跨时钟域的信号通讯,接口部分兼容FPGA的MCB模块,可以实现和MCB的简单替代,最后用verilog语言进行描述并通过仿真验证和FPGA验证,达到了较高的性能和实现了要求的功能。与常见的控制器相比,本设计虽然增加了自测试功能,但综合后的面积只增加10%。

Based on the DDR2 standard developed by JEDEC, this proposed DDR2 controller has a self-test function more for fast testing. The controller has both basic functions include control timing, self-refresh, initialization, and can be tested in the case of no external input pattern. The proposed DDR2 controller is compliance with JEDEC standard, and it follows top-down design flow. The inside signals cross clock domains through asynchronous FIFO. The interface is compatible FPGA MCB module. The controller is finally described by verilog language and verified by simulation and FPGA verification. It achieves high performance and functionality requirements. Compared with the common controller, the design despite has the self-test function more, but the additional area only 10% after synthesis.