期刊文献+

高效容错可逆的汉明码编码和检测电路 被引量:4

Efficient fault tolerant reversible Hamming code encoding and detection circuits
下载PDF
导出
摘要 为了检验传输过程中数据的可靠性,设计了容错可逆的汉明码电路。提出了一种新型的可逆逻辑门(FVG),并且完成了FVG门等价的量子实现。利用FVG门和现有的容错可逆门,实现了汉明码编码电路和检测电路。以(7,4)汉明码设计为实例,根据量子代价和延迟对其进行性能评估,结果证明该电路比现有电路的性能提高10%-20%,仿真实验结果显示,电路逻辑结构正确,性能可靠。 The fault tolerant reversible Hamming code circuits were designed in order to test the reliability of the data in the transmission process. A new reversible gate named four variables parity preserving gate (FVG) was proposed, and the quantum equivalent implementations of FVG was also given. Fault tolerant reversible code encoding and detection circuits were designed using FVG and existing gates. Taking the design of the (7, 4) Hamming code as an example, its circuit performance was evaluated in terms of quantum cost and delay. The results prove that its performance is improved by 10% to 20% than existing counterparts Simulation results indicate that the logic structures of circuit are correct and their performances are reliable
出处 《量子电子学报》 CAS CSCD 北大核心 2013年第5期586-593,共8页 Chinese Journal of Quantum Electronics
基金 安徽省自然科学基金(KJ2010A133) 安徽省高等学校质量工程项目(2012JYXM104)资助
关键词 量子信息 可逆逻辑 容错 汉明码 FVG门 编码和检测 preserving quantum information reversible logic fault tolerant Hamming code four variables parity gate encoding and detection
  • 相关文献

参考文献12

  • 1Landauer R. Irreversibility and heat generation in the computing process [J]. IBM J. Res. Develop., 1961, 5(2): 183-191.
  • 2Bennett C H. Logical reversibility of computation [J]. IBM J. Res. Develop., 1973, 17(6): 525-532.
  • 3Haghparast M. Design and implementation of nanometric fault tolerant reversible BCD adder [J]. Aust. J. Basic & Appl. Sci., 2011, 5(10): 896-901.
  • 4Haphparast M, Mohammad M, Navi K, et al. Optimized reversible multiplier circuit [J]. J. Circuit Syst. Comp., 2009, 18(2): 311-323.
  • 5Mohammadi M, Eshghi M. On figures of merit in reversible and quantum logic designs [C]. Quant. Info. Proc., 2009, 8(4): 297-318.
  • 6Islam M S, Begum Z. Reversible logic synthesis of fault tolerant carry skip BCD adder [J]. J. of Bangladesh Academy of Sci., 2008, 32(2): 193-200.
  • 7吕洪君,彭斐,吴天昊,解光军.非可逆逻辑门的量子可逆实现研究[J].量子电子学报,2009,26(6):668-674. 被引量:6
  • 8Haghparast M. Design and implementation of nanometric fault tolerant reversible BCD adder [J]. Aust. J. Basic & Appl. Sci., 2011, 5(10): 896-901.
  • 9Haghparast M, Dastan F. A novel nanometric fault tolerant reversible divider [J]. Int. J. Phys. Sci., 2011, 6(24): 5671-5681.
  • 10Akbar E P A, Haghparast M, Navi K. Novel design of a fast reversible Wallace sign multiplier circuit in nan- otechnology [J]. Microelectron. J., 2011, 42(8): 973-981.

二级参考文献7

  • 1Feynman R P. Simulating physics with computers [J]. Int. J. Theor. Phys., 1982, 21: 457-488.
  • 2Deutsch D. Quantum theory, the Church-Turing principle and the universal quantum computer [C]. Proc. of Roy. Soc. London A, 1985, 400: 97-117.
  • 3Shor P W. Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer [J]. SIAM Journal on Computing, 1997, 26: 1484-1509.
  • 4Miller D M, Maslov D, Dueck G W. A transformation based algorithm for reversible logic synthesis [C]. Proc. of the 40th Conference on Design Automation, 2003, 318-321.
  • 5Dueck G W, Maslov D, Miller D M. Transformation-based synthesis of networks of Toffoli/Fredkin gates [C]. Proceedings of the 2003 IEEE/A CM International Conference on Computer-aided Design, 2003, 211-214.
  • 6Maslov D, Dueck G W, Miller D M. Fredkin/Toffoli templates for reversible logic synthesis [C]. ICCAD, 2003, 9-13.
  • 7Fredkin E. Toffoli T. Conservative logic [J]. Int. J. Theor. Phys., 1982, 21: 219-253.

共引文献5

同被引文献36

  • 1韩永相,白国强,陈弘毅.有限域上模逆电路的VLSI设计与实现[J].微计算机信息,2008,24(2):1-3. 被引量:4
  • 2吴楠,宋方敏.量子计算与量子计算机[J].计算机科学与探索,2007,1(1):1-16. 被引量:19
  • 3Feynman R. Quantum mechanical computers [J]. Optic News, 1986, 16(6): 11-20.
  • 4Fredkin E, Toffoli T. Conservative logic [J]. International Journal of Theoretical Physics, 1982, 21(3): 219-253.
  • 5Vedral V, Barenco A, Ekert A. Quantum networks for elementary arithmetic operations [J]. Phys. Rev. A, 1996, 54(1): 147-153.
  • 6Maslov D, Dueck G W, et al. Toffoli network synthesis with templates [J]. IEEE Transactions on CAD, 2005, 24(6): 807-817.
  • 7Gupta P, Agrawa A, Jha N K. An algorithm for synthesis of reversible logic circuits [J]. IEEE Transactions on CAD, 2006, 25(11): 807-817.
  • 8Shende V V, Prasad A K, et al. Synthesis of reversible logic circuits [J]. IEEE Transactions on CAD, 2003, 22(6): 723-729.
  • 9Yang G W, Song X, et al. Fast synthesis of exact minimal reversible circuits using group theory [C]. Proceedings of the lOth Asia and South Pacific Design Automation Conference, Shanghai, 2005, 2: 18-21.
  • 10Li Z Q, Chen H W, Xu B W, et al. Fast algorithm for 4-qubit reversible logic circuits synthesis [C]. Proceedings of WCCI 2008, Hong Kong, 2008, 300-306.

引证文献4

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部