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65nm Cu互连晶片边缘和辐射状污染研究

Study on Edge and Radiation Pollution of 65 nm Copper Interconnection Wafer
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摘要 随着Si片尺寸加大和特征尺寸的缩小,对Si片的洁净程度、表面的化学态以及表面缺陷等要求越来越高。针对300 mm 65 nm Cu互连晶片清洗后表面常出现边缘和辐射状污染的问题。在理论分析的基础上,研究了缩短化学药液喷射臂和去离子水喷射臂的间隔时间,实现不同喷射臂无间隔连续喷射技术,并优化化学药液喷射臂的摆臂速度、轨迹和起始终止角度等参数。采用北京七星华创电子股份有限公司自主研发的300 mm 65 nm Cu互连单片清洗机进行工艺实验,结果表明:清洗后晶片表面无边缘和辐射状污染,清洗后晶片表面临界颗粒直径0.12μm,临界颗粒数每片30个;临界尺寸变化不大于2%。 The progressively decreasing feature size and increasing wafer size is driving the demand for cleaning wafer. Conventional cleaning process faces many technical challenges such as wafer cleaning effect, surface chemical conditioning and surface defect. One of the most important issues is the edge pollution and radiation pollution frequently appeared on 300 mm 65 nm copper interconnection wafer surface after cleaning. Based on theoretical analysis, the non-interval continuous injection technology is proposed, which shorten the time of chemical arm and de-ionized water arm intervals. In order to meet the demands of clean process, continuous efforts have been devoted to optimizing process parameters, such as the chemical arm swing speed, trail and initial termination angle. The experiment of optimization process factors is carried out by using Sevenstar Electronics cleaning tool for 300 mm 65 nm copper interconnection. After cleaning, the result indicated that there is no edge and radiation pollution, the count of particles is less than 30 on 0.12 μm diametered critical particle and feature size variation is less than or equal to 2.0%.
作者 刘效岩 吴仪
出处 《半导体技术》 CAS CSCD 北大核心 2013年第9期676-680,共5页 Semiconductor Technology
基金 国家科技重大专项(2009ZX02005-001)
关键词 300 mm SI衬底 65 NM CU互连 边缘和辐射状污染 颗粒度 特征尺寸 300 mm silicon substrate 65 nm copper interconnection edge pollution and radiation pollution particle feature size
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  • 1LAN H B, DINGY C, LIU H Z, et al. Review of the wafer stage for nanoimprint lithography [ J ]. Microelectronic Engineering, 2007, 84 (4): 684-688.
  • 2DELEONIBUS S. Physical and technological limitations of nano CMOS devices to the end of the road map and beyond [J]. EPJ Applied Physics, 2006, 36 (3): 197 - 214.
  • 3SAGA K, HATTORI T. Influence of silicon-wafer loading ambients in an oxidation furnace on the gate oxide degradation due to organic contamination [ J ]. Appl Phys Lett, 1997, 71 (25): 3670 -3672.
  • 4KIM T G, KURT W, PARK J G, et al. Pattern collapse and particle removal forces of interest to semiconductor fabrication process [ J 1. Solid State Phenomena, 2009, 145/146 (1) : 47 -50.
  • 5OHMI T, ISAGAWA T, KOGURE M, et al. Native oxide growth and organic impurity removal on Si surface with ozone-injected ultrapure water [ Jl. J Electrochem Soe, 1993, 140 (3): 804-820.
  • 6LONGFORD A. Chip packaging challenges--a roadmapbased overview [ J ]. Microelectronics International, 2005, 22 (2): 17-20.
  • 7KAZUNARI 1.45 nm/32 CMOS-challenge and perspective [ J 1. Solid-State Electronics, 2008, 52 (9): 1266-1273.
  • 8CHOI K K, IHI H C, SANG J P, et al. Characterization and integration of new porous low-k dielectric ( k < 2. 3 ) for 65 nm technology and beyond [ J ]. Thin Solid Films, 2007, 515 (12): 5025-5030.
  • 9ZSOLT T, KRISTOF C, GERALD P B. Reliability of copper low-k interconnects [J]. Microe|ectronic Engineering, 2010, 87 (3): 348-354.
  • 10PAUL E D, KAUFMAN F, VLASTA B, et al. A model of copper CMP [ J ]. Journal of The Electrochemical Society, 2005, 152 (4): G322-G328.

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