期刊文献+

再布线圆片级封装板级跌落可靠性研究 被引量:5

Study on Board Level Drop Reliability of Wafer Level Packaging with Redistribution Structure
下载PDF
导出
摘要 再布线圆片级封装通过对芯片焊区的重新构造以及无源元件的集成可以进一步提升封装密度、降低封装成本。再布线圆片级封装器件广泛应用于便携式设备中,在实际的装载、运输和使用过程中抗冲击可靠性受到高度重视。按照JEDEC标准对再布线圆片级封装样品进行了板级跌落试验,首先分析了器件在基板上不同组装点位的可靠性差异;然后依次探讨了不同节距和焊球尺寸、再布线结构对器件可靠性的影响;最后,对失效样品进行剖面制样,采用数字光学显微进行形貌表征。在此基础上,结合有限元分析对再布线结构和铜凸块结构的圆片级封装的可靠性和失效机理进行深入地阐释。 Abstract: Wafer level packaging (WLP) with redistribution layers (RDL) could realize high density packaging and cost reduction by relocating the pads over the active area layer and integrating passive components. Wafer level packages are widely applied in portable devices, and during loading, transportation and practical using, the wafer shock resistance have attracted much attention. Board level drop test was conducted on WLP with RDL according to the JEDEC standard, firstly, The reliability of the components assembled at different positions on PCB was analyzed. Then the influences of the RDL structure, pitch size and solder ball size on the reliability of RDL structure WLP devices were studied. Finally, the failed samples were analyzed by the cross-section observation using the digital optical microscopy. Based on the three dimensional finite element model and failure analysis results, the failure mechanism of the RDL and copper pillar structured WLPs caused by drop shock were explained.
出处 《半导体技术》 CAS CSCD 北大核心 2013年第9期702-708,共7页 Semiconductor Technology
基金 国家科技重大专项资助(2011ZX02602)
关键词 圆片级封装(WLP) 再布线层(RDL) 板级跌落 失效分析 有限元分析(FEA) wafer level package (WLP) redistribution layer (RDL) board level drop failureanalysis finite element analysis (FEA) .
  • 相关文献

参考文献12

  • 1刘培生,仝良玉,黄金鑫,沈海军,施建根,朱海清.圆片级封装的研究进展[J].电子元件与材料,2012,31(1):68-72. 被引量:6
  • 2任春岭,高娜燕,丁荣峥.倒装再分布技术及应用[J].电子与封装,2009,9(12):1-4. 被引量:4
  • 3VANDEVELDE B. Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques I J]. IEEE Transactions on Advanced Packaging, 2000, 23 (2): 239-246.
  • 4DESMOND Y R, CHONG F X, CHE L H, et al. Performance assessment on board-level drop reliability for chip scale packages ( fine-pitch BGA ) [C // Proceedings of the 56's Electronic Components and Technology Conference. San Diego, USA, 2006: 356- 363.
  • 5ZHANG X R, ZHU W H, POH E, et al. Study on board level drop reliability of wafer level chip scale pack- age with leadfree solder [ C] // Proceedings of the 10'h Electronics Packaging Technology Conference. Singapore, 2008:1096 -1101.
  • 6LEE J K, PARK Y M, KANG I S, et al. Improvement of drop shock and TC reliability for large die wafer level packages in mobile application [ C] // Proceedings of the 11 th Electronics Packaging Technology Conference. Singapore, 2009:673 - 678.
  • 7TEE T Y, TAN L B, ANDERSON R, et al. Advanced analysis of WLCSP copper interconnect reliability under board level drop test [ C] // Proceedings of the 10'h Electronics Packaging Technology Conference. Singapore, 2008 : 1086 - 1095.
  • 8JESD22 - Blll , Board level drop test method of components for handheld electronic products [ S ]. JEDEC Solid State Technology Association, 2003.
  • 9DHIMAN H S, FAN X J, ZHOU T, et al. JEDEC board drop test simulation for wafer level packages (WLPs) [C] //Proceedings of the 59'h Electronic Components and Technology Conference. San Diego, USA, 2009: 556 - 564.
  • 10叶晓通,陈栋,张黎,李越生,肖斐.圆片级封装的板级跌落可靠性研究[J].半导体技术,2012,37(10):804-809. 被引量:1

二级参考文献29

  • 1何明敏,吴丰顺,张伟刚,吴懿平,安兵.Sn-Ag-Cu焊点IMC生长规律及可靠性研究[J].电子质量,2006(8):25-29. 被引量:3
  • 2FAN X J, VARIA B, HAN Q. Design and optimization of thermo-mechanieal reliability in wafer level packaging [J]. Microeiectron Reliab, 2010, 50: 536-546.
  • 3JUNG G J, PARK Y M. Reliability of various types of wafer level package (WLP) for mobile application [C]//10th EPTC. Singapore: The Conference Organizer, 2008.
  • 4KIM D H, ELENIUS P. Solder joint reliability of a polymer reinforced wafer level package [C]//52nd ECTC. California, USA: The Conference Organizer, 2002.
  • 5PIN Q K, LUDWIG H, WEI Y W. 2nd level reliability drop test robustness for wafer level packages [C] //34th International Electronic Manufacturing Technology Conference. Melaka: The Conference Organizer, 2010.
  • 6KWANG L H. Improving solder joint reliability of WLP by means of a compliant layer [C]//IEMT. Utrajaya, Malaysia: The Conference Organizer, 2006.
  • 7FAN X J. Wafer level packaging (WLP): fan-in, fan-out and three-dimensional integration [C]//11th International Conference on Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems. Bordeaux, France: The Conference Organizer, 2010.
  • 8HUFFMAN A, GARROU P. Manufaeturabillty andreliability study of ALX polymers for WLP applications [C]// 2010 Electronic Components and Technology Conference. Nevada, USA: The Conference Organizer, 2010.
  • 9ZHANG X W, Kripesh V. Parametric design and solder joint reliability analysis of a fine pitch cu post type wafer level package (WLP) [C]//7th Electronics Packaging Technology Conference. Singapore: The Conference Organizer, 2005.
  • 10ZHANG X W, KRIPESH V. Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP) [J]. Microelectron Reliab, 2008, 48: 602-610.

共引文献8

同被引文献79

引证文献5

二级引证文献16

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部