摘要
通过对SATA协议和扰码原理的分析,在串行扰码的基础上,实现了一种基于SATA接口的并行32 bit扰码和解扰算法。数据传输速度快、时延小、更稳定,并行扰码比串行扰码能更好地满足SATA接口的高速传输时序。最后在FPGA上使用VHDL语言编程,对模块进行了验证。
Based on the analysis of SATA protocol and scrambling code principle,a 32 bit-parallel scramble and descramble algorithm for SATA interface from the serial scramble is implemented.Data transmission speed is faster and more stable,the time delay is small.The parallel scrambler can better meet the needs of the SATA interface for high-speed transmission timing than serial scrambler.Finally,using the VHDL programming language in the FPGA,the module is verified.
出处
《电视技术》
北大核心
2013年第19期71-73,90,共4页
Video Engineering
基金
国家自然科学基金项目(61201388)
高等学校博士学科点专项科研基金项目(20110181120009)
