北斗B1I信号码模块的FPGA设计与实现

Design and Implementation of Beidou B1I Signal Code Module on FPGA

基于FPGA技术,设计实现了北斗B1I信号码模块,包括码模块的关键参数设计以及各部分的详细设计.采用模块化设计思想,重点设计码NCO,码产生,码滑动,并使用Verilog语言在FPGA中仿真实现.仿真结果表明:理论分析与实验结果吻合,能够正确高效的产生北斗B1I信号,码跟踪频率分辨率为9mHz,码相位误差为1/2码片.为研制北斗接收机相关器芯片奠定了良好的基础.

The code moudle of Beidou B1Isignal was designed based on FPGA technology,and the working principle,parameter design of the module and the detailed design of each module were described.The code NCO,the code generate and the code slipping were designed by using modular design.All the designs of code module were implemented in Verilog language on FPGA.The simulation results show that Beidou B1Isignal can be generated efficient by this metoil.The error of code tracking frequency is 9mHz.The code phase error is 1/2chip.It shows that the positive result laid a good foundation for the development of correlator chip of Beidou receiver.