音频Delta-Sigma数模转换器中高性能数字前端模块设计

Design of an efficient digital front-end for audio delta-sigma digital-to-analog converter

为适应现代便携式音频设备高音质、微型化与低功耗的要求,提出一种面积优化的高精度delta-sigma数模转换器数字前端模块设计.采用改进型公共子式消除(CSE)算法构建有限冲击响应(FIR)内插滤波器,增加公共子式的利用率,以降低系统硬件开销与芯片面积;并采用一种新型双向循环移位数据加权平均(DCS-DWA)技术,可在不引入寄生音调的前提下抑制三阶四比特量化Delta-Sigma调制器的匹配误差,提高了系统的信噪失真比(SNDR).该模块在中芯国际0.18μm 1P6M标准CMOS工艺下流片,核心芯片面积为0.42mm2,峰值SNDR与动态范围(DR)分别达到103.2dB和104.4dB.在1.5V电源电压下,系统功耗为0.12mW.以上结果表明主要的设计目标均已实现.

An area-efficient and high precision digital front-end of audio delta-sigma digital-to-analog con- verters （DAC） was presented to meet the increasing demands of modern audio equipments on high-fidelity, portability and low power consumption. An improved common subexpression elimination （CSE） method, which increased the utilization rate of common subexpressions and decreased the hardware overhead and die area, was proposed to implement the finite impulse response （FIR） interpolator. Besides, a novel data weighted averaging （DWA） technique named as dual cycle shift DWA （DCS-DWA） was applied to a feed- forward 3 rd-order delta-sigma modulator with a 4-bit quantizer to eliminate the mismatch errors while no signal-dependent tones were introduced into the modulation loop, and as a result the signal-to-noise distor- tion ratio （SNDR） of the system was improved. The prototype of the digital front-end was implemented in a standard SMIC CMOS 0.18 μm 1P6M process, and the core area was 0.42 mm2. The measurement results showed that the peak SNDR of the digital front-end was 103.2 dB, and the dynamic range （DR） was 104.4 dB for the audio signal bandwidth of 20 kHz. In addition, the system power consumption was reduced to 0.12 mW in a supply voltage of 1.5 V. It has been proven that the main experimental results are consistent with the expectations well.