应用于大规模ASIC的线长驱动的合法化算法

Wire-length Driven Legalization Algorithm for Large-scale ASIC

总体布局完成之后的核心任务就是单元位置的合法化,即在将所有的单元安放到布局区并且与合理位置(site)对齐的同时,消除单元间的重叠。为了高效地实现大规模ASIC(Application Specific Integrated Circuit,专用集成电路)的布局过程,提出一种基于线长驱动的合法化算法。它以电路总线长为优化目标,同时考虑单元布局合理位置的约束和预布障碍。在ISPD’11和DAC’12竞赛例子上进行的测试结果表明了算法在线长保护及优化方面的效果。这些测试用例都是来源于现代工业ASIC设计的实例,由此说明了算法可以稳定有效地解决工业界中大规模ASIC多种特征电路的布局合法化问题。

Legalization is core task of the detail placement after global distribution of generous cells. It removes cells overlap, aligns them to the sites and places them to their final position. A wire-length driven legalization algorithm was presented in this paper. The algorithm takes the total wire-length as objective, considers the site cOnstraint and prede- fined blockage. Experiments on ISPD＇ 11 and DAC＇ 12 benchmarks show that this legalization algorithm can get good wire-length results. These test cases are derived from modern industrial ASIC design, which also testify the algorithm can effectively solve the varying characteristics circuit layout legalization issues of large-scale ASIC.