甚高频多普勒雷达的数字前端设计

Design of Digital Front End in VHF Doppler Radar

针对在设计雷达数字接收机过程中,基于查找表法的数字下变频实现占用大量的块存储资源和乘法器硬件资源的问题,提出一种高效、紧凑的CORDIC-DDC实现方案,并进行详细的性能分析。系统测试结果表明,与传统查找表方式相比,无需乘法器,且节约了大于60%的块存储资源,最大运行速度提高38%。

According to the problems of digital down converter based on look-up table,which occupies of a large number of block RAM and hardware multiplier resources,this paper puts forward an efficient and compact CORDIC-DDC architecture for implementation of DDC in FPGA,and the detailed performance analysis is made.Compared to the traditional look-up table implementation,the actual system implementation results show that the multiplier-free method achieves savings of above 60％ of the block RAM resources,and increasing 38％ of the maximum operating speed.