摘要
针对超声波无损检测中检测信号存在噪声干扰这一问题,采用了将乘加运算转化为查找表的并行分布式算法,在FPGA上实现了一个16阶FIR低通滤波器。通过QuartusII进行硬件仿真,仿真结果表明设计的FIR滤波器滤波效果良好,且运行速度较快。
The focus of this paper is to decrease the noise that inpacting the ultrasonic nondestructive testing signals. Using a parallel distributed algorithm which can transfer multiply-add operations into the lookup table to design a 16-step parallel fir filter based on FPGA .The filter was simulated by Quatus II., the hardware simulation result shows that the designed FIR filter is good and run faster.
出处
《电子设计工程》
2013年第19期152-155,共4页
Electronic Design Engineering
关键词
无损检测
FPGA
分布式算法
FIR滤波
查找表
non-destructive testing
FPGA
distributed algorithm
FIR filter
look up table
