摘要
通过建立电源噪声影响I/O信号抖动的方法学,从而打破狭义电源完整性纯粹追求低噪声的设计思路,佐证了电源噪声灵敏度这一概念。搭建锁相环模型仿真绘制出灵敏度曲线,并通过分析,得到不同频率噪声存在互调的结论,对高速串行链路接口设计具有一定指导性意义。
The methodology of the I/O signal jitter affected by power supply noise is presented, which is a breakthrough to the design idea of pure pursuit of low noise for the special power integrity. The concept of jitter sensitivity is verified. The PLL model is used to draw the curve of sensitivity, which suggests that intermodulation exists among different frequency noises.
出处
《电子科技》
2013年第10期101-104,共4页
Electronic Science and Technology
关键词
噪声灵敏度
互调
锁相环
电源完整性
sensitivity of noise
intermodulation
phase locked loop
power integrity
