一种DMOS漏极背面引出的BCD工艺

A BCD Technology with Vertical DMOS

当前BCD工艺中所集成的功率器件的电极都是从芯片表面引出,这会增加芯片面积、引入更多寄生效应、增加高压互连的复杂度.为解决现有BCD工艺存在的缺陷,提出了一种集成有高压VDMOS器件,并将VDMOS的漏极从芯片背面引出的BCD工艺.仿真得到VDMOS的阈值电压为2.5V,击穿电压为161V;NPN管和PNP管的C-E耐压分别为47.32V、32.73V,β分别为39.68、9.8;NMOS管和PMOS管的阈值电压分别为0.65V、-1.16V,D-S耐压分别为17.37V、14.72V.

In current BCD technology, outlets of the circuit are led from top surface of the chip. Therefore, buried layers and sink areas are needed to make good contact and device interconnect. These structures reduce the integration of power chips, and introduce additional resistance and parasitic capacitance, and complicate interconnection especially for high voltage interconnection. In this paper, a new BCD technology was proposed. High voltage VDMOS was integrated in this new technology, and it was designed with the Drain contact on the back. This new technology overcomes the disadvantages of the conventional BCD technology. The simulation results shown that for VDMOS, the threshold voltage is 2.5 V and D-S breakdown voltage is 161 V, for NPN and PNP, C- E breakdown voltage is 47. 32 V and 32. 73 V, 13 is 39. 68 and 9. 8 respectively, for NMOS and PMOS, threshold voltage is 0. 65 V and -1.16 V respectively, D-S breakdown voltage is 17. 37 V and 14. 72 V respectively.