高速可重构插入与抽取单元设计

DESIGNING HIGH SPEED RECONFIGURABLE INSERT AND EXTRACT UNIT

针对序列密码算法中延迟较大的插入与抽取操作,提出基于butterfly和inverse butterfly网络的可重构硬件实现方案,使其支持位宽为2n比特的任意插入与抽取操作。并对控制信息生成算法进行深入的研究,在简化电路硬件实现的同时,大幅度提升了插入与抽取操作的处理性能。该设计已在FPGA上完成功能验证,并在CMOS 0.13μm工艺下完成综合与优化,结果表明,可重构插入与抽取单元延时小于2.7 ns,系统时钟频率达到了450 MHz。

Aiming at the insert and extract operation with bigger delay in stream cipher algorithm, we present the implementation scheme for reconfigurable hardware which is based on butterfly and inverse butterfly network, and allow it to support arbitrary insert and extract opera- tions in widths of 2n bits. We also make thorough study on control bits generation algorithm, while simplify the circuit hardware, the process- ing performance of insert and extract operation is greatly improved as well. The design has been completed its function verification on FPGA and its synthesis and optimisation with CMOS 0.13 μm technology. Result shows that the reconfigurable insert and extract unit has the delay less than 2.7 ns, its system time frequency achieves 450 MHz.