一种数字下变频器中抽取滤波器链的设计与实现

A Design and Implementation of Decimation Filter Chain Used in Digital Down Converter (DDC)

数据抽取是数字下变频器的核心技术之一,抽取滤波器链设计的优劣将直接影响整机的工作性能。文章介绍了总抽取因子为256的抽取滤波器链设计,并用Matlab软件对其性能进行了仿真,最后,在专用数字下变频器HSP50216上构建了该抽取滤波器链。

Data decimating is one of the core technology in digital down converter （DDC）; the performance of receiver can be influenced by the design quality of decimation filter chain. In this paper, decimation filter chain with total decimation factor 256 is presented at first, and then Matlab software is used to simulate the performance of it. Finally, the Scheme is carried out bv digital down convener HSP50216.