基于CCSDS标准的高速LDPC译码算法

High-speed LDPC Decoding Algorithm Based on CCSDS Standard

简要介绍了准循环低密度奇偶校验(LDPC)码的重要性,对CCSDS标准定义的LDPC码进行了深入研究。针对LDPC码的校验矩阵具有稀疏准循环特性,对归一化最小和译码算法进行了研究,给出了部分并行译码器的结构。通过数值仿真验证了译码算法在高斯白噪声条件下的译码性能。利用现场可编程逻辑器件(FPGA)对CCSDS标准中定义的(5120,4096)码进行了实现。

This paper presents the importance of quasi-cyclic Low Density Parity Check Codes （LDPC） ,and studies the LDPC code defined in CCSDS standard. A normalized min-sum （NMS） algorithm is studied considering the parity-check matrix of LDPC codes is sparse and quasi-cyclic. Partly parallel structure of the decoder is given. The performance of the decoder in Gaussian channel is veri- fied by numerical simulation. The （5120,4096） decoder defined in CCSDS is implemented by Field Programmable Gate Arrays （FP- GA）.