期刊文献+

内存测试方法的研究和实现 被引量:2

Research and implementation of Memory test methods
下载PDF
导出
摘要 本文主要讲述内存芯片的测试方法,并在国产集成电路测试系统上完成测试。通过硬件算法图形产生器模块弥补自动测试系统数字通道图形深度不足的问题,该模块具有24位独立地址输出,具有地址装载、保持、加一和减一等功能。采用新March算法,增加多种故障模型,优化编写图形向量,减少其图形深度,提高其故障覆盖率。不仅能加快内存芯片测试的速率,还能保证功能测试的故障覆盖率,对我国内存芯片的测试产生积极的影响。 This paper focuses on the memory chip testing methods,and in the domestic IC test system to complete the test.Graph algorithms generated by the hardware modules make up the digital channel graphics depth automatic test system the problem of insufficient,the module has 24 independent address output,with address loading,hold,plus one and minus one feature.Adoption of the new march algorithm,increase the variety of fault models,optimization prepared graphics vector,reduce its graphical depth,improve its fault coverage.Not only can accelerate the rate of the memory chip testing,but also to ensure functional test fault coverage,testing of memory chips to China have a positive impact.
作者 赵雪莲 杜宇
出处 《国外电子测量技术》 2013年第9期46-51,共6页 Foreign Electronic Measurement Technology
关键词 算法图形产生器 测试向量 自动测试系统 MARCH算法 algorithm pattern generator test vector ATE march algorithm
  • 相关文献

参考文献9

二级参考文献34

共引文献23

同被引文献24

  • 1江建慧,朱为国.嵌入式存储器的内建自测试和内建自修复[J].同济大学学报(自然科学版),2004,32(8):1050-1056. 被引量:12
  • 2KOTHANDARAMAN C, IYER S K, IYER S S, et al. Electrically programmable fuse (eFUSE) using electromigration in silicides[J]. IEEE Electron Device Lett, 2002, 23(9): 523-525.
  • 3GREG U, TONY A, TOSHIAKI K, et al. A commercial field- programmable dense eFUSE array memory with 99. 999% sense yield for 45nm SOl CMOS [J]. Solid-State Circuits Conference, 2008: 406-407.
  • 4RIZZOLO R F, FOOTE T G, CRAFTS J M, et al. IBM system z9 eFIJSE applications and methodology [J]. IEEE IBM J. Res. Dev., 2007, 51(1. 2): 65-75.
  • 5YANG L Y, HSIEH M C, LIU J S, et al. A highly scalable interface fuse for advanced CMOS logic technologies [ J ]. IEEE ELECTRON DEVICE LETTERS, 2012, 33(2).. 245-247.
  • 6SASAKI T, OTSUKA N, LIU J S, et al. Melt- segregate-quench programming of electrical fuse[J]. IEEE International Reliability Physics Symposum Procedings, 2005.. 347-351.
  • 7ITO H, NAMEKAWA T. Pure CMOS one-time programmable memory using gate-ox anti-fuse [J]. CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2004 : 469-472.
  • 8KULKARNI S H, CHEN Z, HE J, et al. A 4 KBmetabfuse OTP-ROM macro featuring 2 V programmable 1.37 μm2 1T1R bit cell in 32 nm high- k metal-gate CMOS [J ]. IEEE J. Solid- State Circuits, 2010, 45(4): 863-868.
  • 9SAFRAN J, LESLIE A, FREDEMAN G, et al. A compact eFUSE programmable array memory for SOl CMOS[J]. IEEE Symposium VLSI Circuits Meeting, 2007: 72-73.
  • 10GEBRESELASIE E G, VOLDMAN S H, HE Z X, et al. Electrically programmable fuses for analog and mixed signal applications in silicon germanium BiCMOS technologies [J]. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007: 238-241.

引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部