单总线传感器接口Verilog的设计与实现

The Design and Implementation of the Single-the Bus Sensor Interface Verilog

嵌入式设备中高速处理器对低速串行总线接口设备通常是使用软件延时来满足低速串行总线接口的时序要求,大大降低了CPU资源的有效利用率。本设计使用CPLD器件作为CPU的协处理器,负责完成单总线设备的数据读取,并转换为并行数据供CPU读取。从而减少CPU读取低速串行总线设备的等待时间。实验中该接口工作稳定可靠,满足设计要求,实验表明该设计方法是行之有效的。

High-speed processor for low -speed serial bus interface device embedded devices usually use software delay to meet the timing requirements of the low-speed serial bus interface , greatly reduces the effective utilization of the CPU resources . Coprocessor design as the CPU using CPLD devices , responsible for the completion of the single -bus device data read and conver-ted to parallel data for CPU to read .Reducing the waiting time of the CPU reads the low-speed serial bus devices .Experiment , the interface is stable and reliable to meet the design requirements , experiments show that the design method is effective .