一种应用于14 bit 200 MS/s电流舵型DAC的数字校准技术

A Digital Calibration Technique for a 14 bit 200MS/s Current-steering DAC

电流舵型数模转换器(DAC)广泛应用于通信系统。采用电流分叉结构的电流舵型DAC可以极大地减小电流源阵列的面积。提出一种可以应用于采用电流分叉结构的电流舵型DAC的数字校准技术。提出的后台校准技术可以同时消除高位电流源阵列和低位电流源阵列的失配误差。基于0.18μm CMOS工艺,设计并流片了一款14bit 200MS/s电流舵型DAC,经过数字校准后,无杂散动态范围(SFDR)能够提高至少24dB。在时钟频率为200MS/s,输出信号为2MHz时,SFDR能够达到80dB以上。芯片面积为1.26mm2,功耗为125mW。

The current-steering digital-to-analog converters （DACs） are widely used for tele- communication applications. The current-splitting architecture can be used for the current-steer- ing DAC to reduce the area of the current source array significantly. A digital calibration tech- nique for the current-steering DAC with the current-splitting array is presented. The proposed calibration technique can eliminate mismatch errors for both the upper bits array and the lower bits array in the background. A 14 bit 200 MS/s current-steering DAC is implemented in a 0.18 ~tm CMOS process. After calibrating, the SFDR （spurious-noise-free dynamic range） can be im- proved by more than 24 dB. The SFDR achieves more than 80 dB at 2 MHz output signal for a 200 MS/s sampling rate. The core area is 1.26 mm2 and power consumption is 125 mW.