低功耗内容寻址存储器的设计

Design of Low Power Content Addressable Memory

分析了传统内容寻址存储器(CAM)结构,提出其功耗模型。根据功耗模型,设计了一种适用于以太网MAC地址识别的新型低功耗CAM单元结构及其预充电路。基于SMIC 0.18μm/1.8V工艺库,利用HSPICE平台对电路进行仿真,仿真频率为100MHz。结果表明,64×64的新型CAM阵列平均查找时间为0.8955ns,写入功耗和查找功耗分别为22.61μW/b和4.186μW/b,仅为传统CAM结构的12.58%和37.9%。

Structure of traditional content addressable memory （CAM） was analyzed, and a power model of CAM was presented. Based on the power model, a novel low-power CAM structure for ethernet MAC address recognition was designed, together with its pre-charge circuit. The circuit was simulated at 100 MHz in SMIC 0. 18μm/1.8 V process using HSPICE. Simulation results showed that the novel CAM cell with 64 - 64 array had an average lookup time of 0. 8955 ns, and a power consumption of 22. 61 μW/bit and 4. 186 μW/bit for writing and looking-up, respectively, which were only 12. 58% and 37.9% of the conventional CAM structure.