摘要
以电流舵型D/A转换器为核心,设计了一个8通道14位60MHz D/A转换器。采用三段电流源(5+4+5)结构的核心D/A转换器单元,有效地保证了转换器的精度和速度;利用电荷泵锁相环进行时钟倍频和多组时钟信号的相位同步,确保电路动态性能;通过输入级引入失调来获得具有迟滞特性的低压差分信号(LVDS)接收器,实现了840 Mb/s高频数据接口功能。电路采用CMOS工艺,在60MHz时钟频率,2MHz模拟输出频率下,功耗小于1 W,无杂散动态范围大于72dB。
An 8-channel 14-bit 60 MHz current steering D/A converter was designed based on current steering architecture. In this circuit, a 3-segment (5+4+5) current source was used to ensure both resolution and speed of the converter; a charge pump PLL was employed to double clock signal frequency and synchronize multiple clock signals, in order to guarantee dynamic performance of the circuit; LVDS receiver with hysteresis characteristics was implemented by introducing offset to input stage, which fUnctioned as 840 Mb/s high frequency data interface with external circuits. Implemented in CMOS process, the D/A converter chip had a power consumption less than 1 W when operating at 60 MHz clock frequency and 2 MHz analog output frequency, and it achieved an SFDR above 72 dB.
出处
《微电子学》
CAS
CSCD
北大核心
2013年第4期508-512,共5页
Microelectronics