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8通道14位60MHz电流舵型D/A转换器

An 8-Channel 14-Bit 60 MHz Current Steering D/A Converter
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摘要 以电流舵型D/A转换器为核心,设计了一个8通道14位60MHz D/A转换器。采用三段电流源(5+4+5)结构的核心D/A转换器单元,有效地保证了转换器的精度和速度;利用电荷泵锁相环进行时钟倍频和多组时钟信号的相位同步,确保电路动态性能;通过输入级引入失调来获得具有迟滞特性的低压差分信号(LVDS)接收器,实现了840 Mb/s高频数据接口功能。电路采用CMOS工艺,在60MHz时钟频率,2MHz模拟输出频率下,功耗小于1 W,无杂散动态范围大于72dB。 An 8-channel 14-bit 60 MHz current steering D/A converter was designed based on current steering architecture. In this circuit, a 3-segment (5+4+5) current source was used to ensure both resolution and speed of the converter; a charge pump PLL was employed to double clock signal frequency and synchronize multiple clock signals, in order to guarantee dynamic performance of the circuit; LVDS receiver with hysteresis characteristics was implemented by introducing offset to input stage, which fUnctioned as 840 Mb/s high frequency data interface with external circuits. Implemented in CMOS process, the D/A converter chip had a power consumption less than 1 W when operating at 60 MHz clock frequency and 2 MHz analog output frequency, and it achieved an SFDR above 72 dB.
出处 《微电子学》 CAS CSCD 北大核心 2013年第4期508-512,共5页 Microelectronics
关键词 电流舵 D A转换器 锁相环 LVDS接收器 Current steering D/A converter PLL LVDS receiver
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参考文献8

  • 1CONG Y H,GEIGER R L.A 1.5-V 14-bit 100-MS/s self-calibrated DAC[J].IEEE J Sol Sta Circ,2003,38(12):2051-2060.
  • 2CHAN K L,GALTON I.A 14 b 100 MS/s DAC with fully segmented dynamic element matching[C]//IEEE Sol Sta Circ Conf.San Francisco,CA,USA.2006:2390-2399.
  • 3CHEN Tao,GIELEN G E.A 14-bit 200-MHz current-steering DAC with switching-sequence post-adjustment calibration[J].IEEE J Sol Sta Circ,2007,42(11) : 2386-2394.
  • 4钟书鹏,谭年熊,沈延钊,廖青.一种12位400MHz电流开关型D/A转换器的设计[J].微电子学,2006,36(4):476-479. 被引量:5
  • 5HUANG Q T,FRANCESE P A,MARTELLI C,et al.A 200 MS/s 14 b 97 mW DAC in 0.18 μm CMOS[C]// IEEE Int Sol Sta Circ Conf.San Francisco,CA,USA.2004:532-364.
  • 6朱冬梅,傅东兵,石建刚,杨卫东,刘伦才,李开成.一种用于高精度D/A转换器的数字校准技术[J].微电子学,2010,40(1):24-28. 被引量:3
  • 7拉扎维.模拟CMOS集成电路[M].陈贵灿,等译.西安:西安交通大学出版社.2003:452-458.
  • 8HUANG Xingfa,LI Liang,ZHANG Zhengping,et al.A 0.35 μn CMOS process-based 2.4 Gb/s LVDS for high-speed DAC[C]//长沙,中国.IEEE 8th Int Conf ASIC.2009:317-319.

二级参考文献9

  • 1VAN DEN BOSCH A. High-resolution high-speed CMOS current-steering digital-to-analog converters [M]. Boston: Kluwer Academic Press, 2004.
  • 2SANSEN W M C. Analog Design Essential [M]. Dordrecht: Springer, 2006.
  • 3SCHOFIELD W, MERCER D, ST ONGE L. A 16 b 400 MS/s DAC with <-80 dBc IMD to 300 MHz and <-160 dBm/Hz noise power spectral density [C] // IEEE Int Sot Sta Circ Conf. 2003: 126-127.
  • 4MERCER D A. Low-power approaches to high-speed current-steering digital-to-analog converter in 0. 18 μm CMOS [J]. IEEE J Sol Sta Circ, 2007, 42(8): 1688-1698.
  • 5Van den Bosch A,Steyaert M,Sansen M.SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters[A].Proc 6th IEEE Int Conf Electronics,Circuits and Systems[C].Pafos,Cyprus.1999,3:1193-1196.
  • 6Lee S-C,Cho M-H,Yo H-K.10 bit 200 MS/s CMOS D/A converter employing high-speed limiter[J].Elec Lett,2002,38(23):1407-1408.
  • 7Gustavsson,Wikner J J,Tan N N.CMOS data converters for communications[M].Boston:Kluwer Aca-demic Publishers,2000.
  • 8O'Sullivan K,Gorman C,Hennessy M,et al.A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm2[J].IEEE J Sol Sta Circ,2004,39(7):1064-1072.
  • 9Geert A,Van der Plas M,Vandenbussche J,et al.A 14-bit intrinsic accuracy Q2 random walk CMOS DAC[J].IEEE J Sol Sta Circ,1999,34(12):1708-1718.

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