基于FPGA的高速FIR滤波器的设计与实现

Design and Implementation of a High Speed FIR Filter Based on FPGA

对FIR滤波器中的乘法如何在FPGA得到高效实现进行了研究。结合FPGA查找表结构,兼顾资源和速度的要求,采用改进的分布式算法,设计了20阶常系数FIR滤波器。在此基础上,用OBC编码对其查找表进一步优化。最后,在ISE13.1下进行综合,并在Modelsim下进行仿真,用Matlab分析得到的数据频谱,以确定达到设计效果。结果表明,该设计既节省了FPGA的资源占用,又提高了运行速度。

Efficient implementation of multiplication of finite impulse response （FIR） filter in FleA was studied. A 20-tap constant coefficient FIR filter was designed based on improved distributed arithmetic and offset binary coding （OBC） with FPGA look up table structure Resources and speed requirements were considered in the design. Finally, the design was synthesized using ISE 13. 1 and simulated with Modelsim. Data spectrum was analyzed with Matlab. It has been demonstrated that the design not only saved utilization of FPGA resources, but also improved operating speed.