低比导通电阻P埋层SOI双介质槽MOSFET

A Very Low Specific On-Resistance SOI Double-Trench MOSFET with P-Type Buried Layer

提出了一种带P型埋层的新型SOI双介质槽MOSFET。通过在SOI层底部引入P型埋层作为补偿,在耐压优化情况下增加漂移区的浓度,降低了比导通电阻。MEDICI TCAD仿真结果表明:在281V击穿电压下,该结构的比导通电阻为4.6mΩ.cm2,与不带P型埋层的结构相比,在达到同样耐压的情况下,比导通电阻降低了19%。

A new SOI double-trench MOSFET with P-type buried layer was proposed. Owing to P-type buried layer at the bottom of SOI layer, doping concentration in the drift region increased, which led to a reduced specific on-resistance （Ron,sp）. Results from simulation with MEDICI TCAD showed that the proposed structure had a specific on-resistance of 4. 6 mΩ · cm^2 for a breakdown voltage of 281 V, which was a 19% of reduction, compared to the same structure without P-type buried layer for a comparable breakdown voltage.