连续相位调制解调器的FPGA实现

Implementation of CPM Modem Based on FPGA

针对连续相位调制解调硬件实现复杂度高的问题,提出一种基于FPGA的低复杂度硬件实现方案。该方案中,调制器采用查表法,解调器采用Max-Log-MAP算法。该方案具有复杂度低、速度快、易于生成IP核等优点。利用Xilinx公司的Virtex-2Pro系列开发板,对调制解调器进行测试,验证了该系统方案的正确性。该设计可作为连续相位调制解调专用集成芯片开发的参考。

In view of the high complexity in hardware implementation of the continuous phase modem, a hardware implementation scheme based on FPGA was proposed, in which look-up table method and Max-Log-MAP algorithm were used for modulator and demodulator, respectively. The scheme featured low complexity, high speed and easy generation of IP core. The modem was tested based on Virtex-2 Pro series development board of Xilinx. Test results validated the proposed scheme The design could be used as a reference for development of continuous phase modem IC.