嵌入式I^2C从机设计验证与版图实现

Design Verification and Implementation of Embedded I2C Slave Circuit

提出了一种嵌入式标准化I2C从机设计方案,对传统I2 C从机的状态机进行简化,得到了改进型状态机。综合结果表明,与传统状态机相比,改进型状态机的面积减少约20%,功耗降低约4%。以一款芯片为例,详细介绍了I2 C总线嵌入式开发过程。该方案已通过功能仿真、FPGA验证及版图后仿真。对该电路进行FPGA验证,构建了一种简单、高效的FPGA验证系统。

An embedded standardized I^2C slave circuit was presented. Traditional state machine for slave I^2C bus was simplified, and a modified state machine was obtained. Synthesis results showed that the modified state machine had an area reduction of about 20% and power reduction of about 4%, compared with traditional state machine. With a chip as an example, development process of I^2C bus embedment was described in detail. The circuit design passed behavioral simulation, FPGA verification and post-layout timing simulation. Finally, an easy and efficient method for FPGA verification was constructed to validate the circuit.