一种具有高线性度MOS采样开关的采样保持电路

A Sampling and Hold Circuit with High Linearity MOS Switch

提出了一种具有高线性度MOS采样开关的采样保持电路。该电路通过运放的共享,在采样阶段对开关管的栅极引入负反馈,有效地抑制开关导通电阻引入的非线性,实现了高性能的采样保持电路。该电路采用SMIC 0.13μm标准CMOS工艺设计,仿真结果表明:在采样阶段,导通电阻大约只有0.2Ω的变化;在采样时钟为80 MHz,输入信号为30 MHz、0.5V pp时,无杂散动态范围(SFDR)达到了116 dB,比传统自举开关的SFDR提高了34 dB。

This paper presents a sample /hold circuit,which includes a high linearity MOS switch. Through the opamp sharing used in the sample / hold circuit,it can introduce a feedback voltage to the gate of the sampling switch during its sampling phase,and the feedback voltage can remarkably reduce the non-linearity introduced by on-resistance of the sampling switch. Therefore it can achieve a high performance sample / hold circuit. Based on SMIC 0. 13μm standard CMOS process,the sample/hold circuit is designed,and simulation results show that at sampling phase,the on-resistance of the sampling switch is only 0. 2 Ω variation; and at the 80 Msample / s sample rate,30 MHz and 0. 5V pp input signal,simulation results show that the spurious free dynamic range（ SFDR） achieve116 dB,which is about 34 dB over the conventional switch.