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基于FPGA的某型测控台电路改造设计研究

Study of design and test on FPGA to the practical work of some apparatus circuit
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摘要 本文结合某型测控台电路改进设计的实践工作对FPGA电路的设计、测试方法进行研究,并对其中的关键问题进行了分析。结果表明采用FPGA器件对某型测控台电路集成化,可以提高电路的稳定性,并大大降低了制板成本。 This thesis studies the design method and test according to the practical work of some radar circuits.It also analyses the related important questions which require to be resolved after lots of experiments.FPGA apparatus integrated with MSI and SSI can greatly improve the stability and security of circuits,and reduce the cost.
出处 《仪器仪表用户》 2013年第5期58-60,共3页 Instrumentation
关键词 FPGA 电磁兼容 优化设计 FPGA EMC optimization design
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参考文献9

  • 1Rose J,Francis R J,Lewis D,et al.Architecture of field programmable gate arrays:The effect of logic functionality on area efficiency[J].IEEE J Solid-State Circuits,1990,25(5):12-17.
  • 2Kouloheris J,Gamal E1 A.FPGA area versus cell granularity lookup tables and PLA cells.First [C].Berkeley,CA,ACM Workshop on FPGAs,1992:9-13.
  • 3Singh S, Rose J,Chow P et al. The effect of logic block architecture on FPGA performance [J].IEEE JSSC, 1992,27(3):281-287.
  • 4Ahmed E,Rose J.The effect of LUT and cluster size on deep Submicron FPGA performance and density [J].IEEE Trans Very Large Scale Integration (VLSI)Systems,2004,12(3):288.
  • 5Spartan-Ⅱ 2.5V FPGA Family Complete Data Sheet[M].USA:Xilirnx Inc, 2004:2-3.
  • 6陈冬.基于FPGA的某型雷达电路集成化研究[D].武汉:海军工程大学,2007:32-34.
  • 7徐新民 ,尚丽娜 ,严晓浪 .FPGA的布线结构参数Fc对其功耗的影响[J].高技术通讯,2005,15(10):16-20. 被引量:1
  • 8楼观涛,马跃.FPGA设计中毛刺信号的产生及消除[J].电子世界,2004(7):32-33. 被引量:3
  • 9刘鲭洁,刘晓方,陈桂明.屏蔽在电磁兼容设计中的应用[J].电子质量,2006(10):65-67. 被引量:2

二级参考文献12

  • 1黄海源.电子设备的电磁场屏蔽[J].岳阳职业技术学院学报,2001,18(4):59-61. 被引量:4
  • 2Poon K, Yah A, Wilton S J E. A Flexible Power Model for FPGAs. In: 12^th international Conference on Field-Programmable Logic and Applications, Sept 2002, 312.
  • 3Chen C, Sarrafzadeh M. Provably Good Algorithm for Low Power Consumption with Dual Supply Voltages. In: Proceedings of the 1999 international Conference on Cpmputer Aided Design, 1999. 76.
  • 4LI F, Lin Y, He L, et al. low-Power FPGA Using Pry-defined Dual-Vdd/Dual-Vt Fabrics. In: ACM International Symposium on FPGA, February 2004. 42.
  • 5Li F, Chen D, He L, et al. Architecture Evaluation for Power-Efficient FPGAs. In: ACM International Symposium on FPGA, February 2003. 175.
  • 6Brown S, Francis B, Rose J, et al. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 1992.
  • 7Rose J, EI A, Sangiovanni-Vincentelli Gamal A. Architecture of Field-Programmable Gate Arrays. In: Proceedings of the IEEE. Julv 1993.1013.
  • 8Ahmed E, Rose J. The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density. In: ACM International Symposium on FPC, A, 2000. 3.
  • 9Rose J, Brown S. Flexibility of Interconnection Structures for Field-Programmable Gate Arrays. In: JSSC, March 1991.277.
  • 10Brown S, Khellah M, Lemieux G. Segment Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. Journal of VLSI Design, 1996, 4(4) :275.

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