协作多点传输中板间串行高速通信的FPGA设计

The SRIO FPGA design for interconnect of backbone in CoMP

针对IMT-Advanced协作多点传输试验床中对串行高速通信接口SRIO的应用需求,分析了背板间SRIO通信的FPGA设计关键点。仿真与实测结果表明,设计的SRIO接口可实现全双工可靠通信,数据速率达到6.67 Gb/s。

In order to meet the need of SRIO for IMT-Advanced CoMP test-bed, this paper presents the key FPGA design on inter-backbone SRIO communication. Simulation and test results show that design of SRIO interface can achieve full duplex re- liably communication with high rate of 6.67 Gb/s.