期刊文献+

高精度电流偏置电路的设计

Design of a high precision reference current bias circuit
下载PDF
导出
摘要 提出了一款应用于RF无线收发芯片的高精度电流偏置电路。综合考虑功耗、面积和失调电压对基准电压的影响,设计了一款符合实际应用的带隙基准电路。并以带隙基准电路作基准电流源的偏置,采用电压电流转换器结构设计了具有高电源电压抑制比(PSRR)的基准电流源。电流镜采用辅助运放的设计方法来提高电流镜的输出阻抗,减小沟道调制效应对输出的基准电流的影响,从而提高输出基准电流的精度。采用0.35μm CMOS工艺设计芯片版图,版图面积为0.18 mm2。提取寄生参数(PEX)仿真结果表明,该电路在-55℃^+90℃范围内的温度系数为15.5 ppm/℃,室温下基准电压为1.203 5 V;在低频段电流源的电源抑制比为90 dB;在外接电阻从1 kΩ~400 kΩ变化时,输出基准电流误差范围是0.000 1μA。 A high accuracy current bias circuit is presented in this paper, which can be used in RF wireless transceiver chip. This paper designs a practical application of the bandgap reference circuit, with consideration of the power, area and offset voltage. This paper adopts the bandgap reference circuit and a voltage to current converter structure to design a high power supply rejection ratio design (PSRR) of the reference current. Current mirror with auxiliary operational amplifier (gainboost) is to improve the output impedance, and to reduce the influence of modulation effect on the reference current, so as to improve the precision of output current reference.The reference current bias is simulated based on 0.35 μm technology standard CMOS process. The layout area is 0.18 mm2. Planning parameters extraction (PEX)simulation results show that the reference voltage is 1.203 5 V, temperature coefficient in the range of -55℃~+90℃ is 15.5 ppm/℃, the power supply rejection ratio in low frequency is 90 dB, when the outside resistor is from 1kΩ~400kΩ, the output reference current error range is 0.000 1 μA.
作者 蒋本福 杨骁
出处 《微型机与应用》 2013年第19期29-31,共3页 Microcomputer & Its Applications
基金 福建省自然科学基金(2010J05135) 厦门市科技计划项目(3502Z0113015) 华侨大学基本科研业务费专项基金(JB-ZR1128)
关键词 基准电流 电流镜 版图 reference current mirror current layout
  • 相关文献

参考文献6

  • 1FIORI F, ROVETFI P S. Compact temperture-compensated CMOS current reference[J]. Electronics Letters, 2003,39(1): 724-728.
  • 2BADILLO D A. 15V CMOS current reference wilh extenged temperature operating range[C]. IEEE International Symposium on Circuits and System, ]SCAS 2002, 2002:197-200.
  • 3拉扎维.模拟CMOS集成电路设计[M].陈贵灿,译.西安:西安交通大学出版社,2003.
  • 4ELDBIB I, MUSIL V. Self-cascode current controlled CCII based-tunable band pass filter[C]. 18th International Conference on Radioelektronika, 2008:24-25.
  • 5周玮,吴贵能,李儒章.一种高电源抑制比CMOS运算放大器[J].微电子学,2009,39(3):340-343. 被引量:4
  • 6ZEKI A, KUNTMAN H. Accurate and high output impedance current mirror suitable for CMOS curren| output stages [J]. IEEE 1997 Electronics [/etters,1997,33 (12), 1042-1043.

二级参考文献6

  • 1RIBNER D B, COPELAND M A. Design techniques for cascoded CMOS op-amps with improved PSRR and common-mode input range [J]. IEEE J Sol Sta Circ, 1984, 19 (6). 919-925.
  • 2AHUJA B K. An improved frequency compensation technique for CMOS operational amplifiers [J]. IEEE J Sol Sta Circ, 1983, 18(6): 629-933.
  • 3MIKKO L, JUHA K. PSRR improvement technique for amplifier with Miller capacitor [C]// Int Syrup Cite and Syst. 2006, 1394-1397.
  • 4STEYAERT M S J, SANSEN W M C. Power supply rejection ratio in operational transconductance amplifiers [J]. IEEE Trans Circ and Syst, 1990, 37 (9): 1077-1084.
  • 5ALLEN P E,HOLBERG D R.CMOS模拟集成电路设计[M].冯军,等译.第二版.北京:电子工业出版社,2005:228,611.
  • 6吴贵能,周玮,李儒章.一种基于跨导电流比-反型系数-过驱动电压的设计方法[J].微电子学,2008,38(5):656-659. 被引量:3

共引文献26

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部