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MRU Cache替换算法平均性能剖析

Dissection of the Average-Case Performance of MRU Cache Replacement Policy
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摘要 研究了MRU替换算法的平均性能问题.研究结果发现,在一定条件下,MRU的平均性能优于LRU替换算法.针对具有线性访问序列循环体的程序,形式化证明了MRU平均性能优于LRU的成立条件.并采用实时系统时间分析测试集针对不同Cache配置进行实验,验证了MRU平均性能优于LRU这一结果的普遍性.结合本文结果与MRU实时性能的研究结果,可以认为MRU具有优异的平均性能和实时性能. Cache is a processor feature that can greatly affect the performance of programs. The average-case performance of most recently used (MRU) Cache replacement policy was studied. Research results showed that MRU outperforms LRU in some circumstances. By analyzing loop structures with sequential memory accesses, the condition for this phenomenon is given and formally proved. Extensive experiments were conducted on real-time timing analysis benchmarks for different Cache configurations, which shows that MRU outperforms LRU in lots of execution scenarios. Combining this result and recent results on the real-time performance of MRU replacement policy, it can be concluded that MRU has very high performance in both average-case and real-time metrics.
出处 《东北大学学报(自然科学版)》 EI CAS CSCD 北大核心 2013年第11期1554-1557,共4页 Journal of Northeastern University(Natural Science)
基金 国家自然科学基金资助项目(61100023) 辽宁省博士启动基金资助项目(20111003) 中央高校基本科研业务费专项资金资助项目(N120404008)
关键词 MRU CACHE 替换算法 平均性能 实时性能 MRU( most recently used) Cache replacement policy average-case performance real-time performance
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参考文献10

  • 1Patterson D A, Hennessy J L. Computer architecture: a quantitative approach [ M] 5th ed. Burlington: Morgan Kaufmann Press ,2011:72 - 131.
  • 2AI-ZoubiH, Milenkovic A, Milenkovic M. Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite[ C ]//The 42nd Annual Southeast Regional Conference. Huntsville ,2004 : 267 - 272.
  • 3Wilhelm R, Engblom J, Ermedahl A, et al. The worst-case execution time problem-overview of methods and survey of tools E J ]. ACM Transaction on Embedded Computing Systems ,2008,7 ( 3 ) : 1 - 53.
  • 4Wilhelm R, Grund D, Reineke J, et al. Memory hierarchies, pipelines and buses for future architectures in time critical embedded systems E J ]. IEEE Transactions on CAD of Integrated Circuits and Systems,2009,28 ( 7 ) : 966 - 978.
  • 5Guan N,Lyu M, Wang Y, et al. WCET analysis with MRU cache : challenging LRU for predictability [ C ]//18 th Real- Time and Embedded Technology and Applications Symposium. Beijing ,2012:55 - 64.
  • 6Guan N, Yang X, Lyu M, et al. FIFO cache analysis for WCET estimation: a quantitative approach [ C ]//Design, Automation, and Test in Europe. Grenoble,2013:296 - 301.
  • 7Cullmann C. Cache persistence analysis: a novel approach- theory and practice [ C ]//Conference on Languages, Compilers and Tools for Embedded Systems. Chicago ,2011 : 121 - 130.
  • 8Reineke J, Grund D, Sensitivity of cache replacement policies [ J]. ACM Transactions on Embedded Computing Systems, 2012,9(4) :1 -39.
  • 9Austin T, Larson E, Ernst D. SimpleScalar : an infrastructure for computer system modeling[ J ]. Computer, 2002,35 ( 2 ) : 59 - 67.
  • 10Gustafsson J, Betts A, Ermedahl A, et al. The milardalen WCET benchmarks :past,present and future [ C ]//Workshop on WCET Analysis. Brussels,2010 : 136 - 146.

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