摘要
为了提供网络精细化管理、提升服务质量及加强安全保障,提出了适用于IP骨干网核心路由器的硬件业务识别系统架构,并针对流跟踪管理器日益成为性能瓶颈的问题,设计了基于定长桶的流表结构用于维护存储于片外DRAM的大规模活跃流信息。为了进一步提高系统处理速度,一部分片内高速存储资源被设计为流高速缓存。FPGA实验结果表明,相对不带高速缓存的结构,两级存储结构的流跟踪管理器仅用576kb片内存储空间,提高了188%的处理速度并降低了约40%的功耗,实现了72MPPS的处理速度,使业务识别系统可满足100G链路在平均包长为200字节情况下的速率需求。
To provide meticulous network management, high quality service and security, a hardware-based high speed service identification system architecture is proposed for routers in backbone network. As the flow tracking system becomes the performance bottleneck, a fixed length bucket based flow table is designed to track millions of flows stored in the external DRAM. To further accelerate the tracking system, part of the on-chip SRAM resources are designed to cache the elephant flows. The experiment tested with Altera FPGA shows that the throughput of proposed flow tracking system can be increased by 188% with the power consumption reduced by 44%, which can achieve 72MPPS throughput, enabling service identification system to satisfy 100G link speed with the average packet size of 200 byte.
出处
《计算机工程与设计》
CSCD
北大核心
2013年第11期3780-3784,共5页
Computer Engineering and Design
基金
国家自然科学基金项目(61073171)
清华大学自主科研课题
教育部博士点基金项目(20121080068
20100002110051)