应用多项式插值的流水线ADC后台数字校正方法

Pipeline ADC Background Calibration Applying Polynomial Interpolation

为了降低传统流水线型模数转换器(ADC)中的采样,保持运算放大器和级间的余量放大器功耗,将级间余量放大器由闭环工作方式改为开环,对于使用开环放大器引入的非线性误差,提出一种新颖的后台校正方式.首先对开环放大器建立传输函数模型;然后利用信号传输的统计规律、采用多项式插值法来估计校正误差,将所得的误差值补偿给实际的传输函数值来实现后台校正.以一个12位、40MHz的数字辅助流水线ADC为原型进行了仿真验证,结果表明,当输入信号频率为117.2kHz时,采用数字校正后,ADC系统的微分非线性由(-0.5,0.5)提高到(-0.25,0.25),积分非线性由(-18,0.5)提高到(-0.5,0.25),无杂散动态范围和信噪失真比分别由48.5dB和42.6dB提高为78.9dB和72.3dB,校正后ADC的有效位数达到11.7位.

To alleviate power consumption of sample and hold operational amplifier and inter-stage residual amplifiers in traditional pipeline analog to digital converter （ADC）, the residual amplifiers can work at open-loop mode instead of closed-loop mode. For the nonlinear errors introduced by open-loop amplifier, a novel background calibration method is presented in this paper. First, transfer function model of the open-loop amplifier is established, statistical characteristic of signal transportation is applied to achieve polynomial interpolation, nonlinear error is estimated and compensated to achieve the calibration. To verify the effect of the calibration, simulation is done in a t2 bits, 40 M sample rate pipeline ADC. The experimental results show that, with 117.2 kHz input signal, by applying calibration, differential nonlinearity of the ADC improves from （-0.5,-0.5） to （-0.25,-0.25）, integral nonlinearity improves from （-0. 18,-0. 5） to （-0. 5,-0.25）, spurious free dynamic range and signal to noise and distortion ratio improve from 48.5 dB and 42.6 dB to 78.9 dB and 72.3 dB, the effective number of bits of the ADC reaches 11.7 bits.