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SRAM型大规模FPGA的抗单粒子翻转设计与试验验证 被引量：1

Design and Experiment Demonstration of SEU-tolerant for SRAM-based FPGA
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摘要 对SRAM型大规模FPGA进行了抗单粒子翻转(SEU)设计研究,提出了具体的有效减弱单粒子翻转效应影响的设计方法,并利用兰州重离子加速器(HIRFL)束流终端开展了单粒子效应模拟实验,对设计方法的有效性进行了试验验证。为星载信号处理机的抗单粒子翻转设计提供了参考依据。 This paper presents a single event upset（gEU）-tolerant design method of SRAM I^PGA, which re- duces the SEU effect effectively. It is proved to be a valid design method by simulation experiment of SEU ef- fect with a beam terminal by Heavy Ion Research Facility in Lanzhou （HIIKFL）. It is a reference for SEU-tol- erant of space-based signal processor.
作者 张朝晖 邓明 陈贺贤 李文华
机构地区 中国电子科技集团公司第三十六研究所
出处 《通信对抗》 2013年第3期40-42,62,共4页 Communication Countermeasures
关键词 FPGA 抗单粒子翻转 三模冗余(TMR) 定时刷新 EDAC 单粒子翻转辐照试验 FPGA SEU-tolerant TM1Z timed refreshing EDAC SEU irradiation test
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献4

  • 1邢克飞,杨俊,王跃科,肖争鸣,周永彬.Xilinx SRAM型FPGA抗辐射设计技术研究[J].宇航学报,2007,28(1):123-129. 被引量：51
  • 2NASA JPL.Xilinx Single Event Effects, 1st Consortium Report, Virtex-Ⅱ Static SEU Characterization[]..2004
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二级参考文献11

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