摘要
给出了一种用大规模可编程逻辑器件实现的全数字锁相环 (DPL L )及其性能分析和具体的实现电路。
In this paper,digital PLL with programmable logic device is introduced and its performance analysis and detailed circuit are described.
出处
《四川通信技术》
2000年第6期9-11,共3页
Sichuan Communications Technology