高阶互连网络拓扑结构性能分析与研究

Survey and evaluation of high-radix topology in high performance interconnection network

高性能计算机峰值性能的不断攀升给高性能互连网络带来新的挑战;同时,串行传输技术的发展使芯片引脚带宽增长,使用高阶路由器应对高性能互连网络新挑战的时机已经成熟。因此,如何利用高阶路由器所提供的丰富互连端口提升高性能互连网络的性能和减少高性能互连网络开销是设计高性能互连网络拓扑结构的关键。针对目前基于高阶路由器的典型拓扑结构进行了理论分析,并与传统k元n立方体进行了对比分析。通过在一个基于OMNeT++平台自组开发的高阶互连网络性能测评模拟器上设定不同的通信负载,测评分析了不同的拓扑结构在通信系统下实际的网络延迟和吞吐率的走势,简要分析了典型高阶互连网络拓扑结构的局限性。

With the increasing peak performance of the high performance computers, high performance in- terconnection network is facing more design challenges. Enabled by advancements in high bandwidth serial transport technology and pin bandwidth, high performance interconnection network paves the way for high-radix network. How to utilize high-radix router providing more design choices is the key for high performance net- work topology. The paper studies several typical high-radix topologies. We analyze the performance and cost of those high-radix networks theoretically and compare them with common low-radix topologies. A high-radix in- terconnection network simulator, named xNetSim, is explored to evaluate these topologies, xNetSim is built in the OMNeTq--t- platform. In the simulation, the network loads is varied and the throughput and latency of dif- ferent topologies are verified. At last, the performance gaps between these kinds of high-radix interconnection network topologies are briefly analyzed.