一种基于FPGA的数字延迟器的设计与实现

Design and Implementation of FPGA Based Digital Delayer

延迟器在广播电视等领域用途十分广泛,利用FPGA芯片EP2C70F672C8设计并实现一种数字延迟器,模拟信号经AD转换后,通过乒乓读写操作送入2片SRAM芯片进行存储,然后送DA转换器恢复出延迟后的模拟信号,调节SRAM的存储深度,可以对模拟信号实现不同的延迟时间。实际测试表明,该延迟器延迟步进精度可达20 ns,最大延迟时间可达5.2 ms。

Delayer is widely used in television and other fields. A digital delay system is designed and implemented based on EP2C70F672C8 in this paper. The analog signal is converted to a digital signal by an AD converter and stored in two SRAM memory chips. The SRAM is working on ping-pong operation mode and a delayed analog signal is recovered by DA converter. The delay time can be adjusted by increasing or decreasing of SRAM memory depth. The experimental results show that the 20 ns step-delay time and 5.2 ms longest-delay time is achieved.