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基于边界扫描技术的抗混淆自适应测试算法

Anti-Confounding Adaptive Test Algorithm Based on Boundary Scan Test Technology
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摘要 针对现有边界扫描测试快速测试算法存在征兆混淆现象的问题,在深入分析多种测试算法的基础上,提出一种抗混淆的自适应测试算法。首先,通过分析走步算法的特点,给出一种走步算法的改进方案。该方案在保证算法完备性指标不变的情况下,提高了算法的紧凑性指标。在此基础上,结合改良计数序列算法,生成抗混淆自适应测试算法。该算法解决了改良计数序列算法存在的征兆混淆问题,极大提高了算法的完备性指标,且紧凑性指标较好。 Based on in-depth analysis of various test algorithms, an optimized and adaptive test algorithm is proposed to solve the symptom-confounding problem of rapid test algorithm in boundary scan testing. First, an improved scheme of walking algorithm is given based on the analysis of characteristics of the walking algorithm. In the case of the same algorithm completeness, this scheme can improve the compart index of the algorithm. And then combined with improved counting sequence algorithm, a anti-confounding adaptive testing algorithm is proposed. This algorithm solves the aliasing problem with the modified counting sequence algorithm, and improves the completeness indicators greatly, while the compact index is good.
机构地区 信息工程大学 [
出处 《信息工程大学学报》 2013年第5期600-606,共7页 Journal of Information Engineering University
基金 国家863计划资助项目(2009AA01Z434)
关键词 边界扫描技术 测试算法 紧凑性指标 完备性指标 boundary-scan test technology test algorithm compact index completeness indicators
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  • 1牛春平,常天庆,陈圣俭,任哲平.应用边界扫描技术提高电路板可测试性的两种优化问题[J].微电子学与计算机,2004,21(11):43-46. 被引量:2
  • 2尚玉玲,颜学龙,雷加,李春泉.遗传算法的板级边界扫描测试矢量优化及应用[J].计算机工程与应用,2004,40(20):205-207. 被引量:2
  • 3Test Technology Technical Committee of the IEEE Computer Society. IEEE Std.1149.1-1990 IEEE Standard Test Access Port and Boundary Scan Architecture[S]. 1990.
  • 4Myers M. A Solution for Boundary-scan Test[J]. Asian Electronics Engineer, 1991, 17(4): 236-241.
  • 5胡政.[D].长沙:国防科技大学机电工程及自动化学院,2000.
  • 6A Hassan, J Rajski and V K Agarwal. Testing and Diagnosis of Interconnects using Boundary Scan Architecture.Infl Test Conf, 1988: 126-137.
  • 7Najmi Jarwala and Chi W Yau. A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects. Infl Test Conf, 1989: 63-70.
  • 8P Goel and M T McMahon. Electronic Chip in-place Test.Infl Test Conf, 1982: 83-90.
  • 9L YUngar. Hierarchical Built-In Test: An Alternative Test and Report Strategy. IEEE AUTOTESTCON, 1995:456-463.
  • 10P T Wagner. Interconnect: Testing With Boundary Scan.Intl Test Conf, 1987: 52-57.

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