低功耗并行MIMO空间复用检测器的VLSI结构

Low power parallel VLSI architecture for spatially multiplexed MIMO detection

针对2×2天线配置的多输入多输出无线通信系统,提出了一种新颖的近最大似然多输入多输出检测算法.此算法只对搜索树的第2层节点耗尽搜索,第1层应用区域判定法直接得到假设星座点和反假设点,不需要对每一层搜索树的部分欧几里得距离排序,降低了计算复杂度,而且适合并行处理.依据该算法设计了规则的、流水线型的超大规模集成电路,可以配置并行检测核的数目,从而可灵活地控制吞吐率.在40nm的工艺下,约束工作电压为1.08V,设定时钟频率为156MHz,版图实现可以达到312Mbit/s的吞吐量和23mW的功耗,处理延迟仅为0.051ns.

This paper proposes a novel maximum likelihood-like detection algorithm for the 2×2 MIMO wireless communication system. Only the second layer in the search tree needs to be verified exhaustively, and then the area determination strategy is applied to the first layer to figure out the hypothesis node and counter-hypothesis nodes without sorting the partial Euclidean distance for each layer, which reduces the complexity significantly and leads to parallel implementation. The regular VLSI architecture is designed according to the detection algorithm, and flexible parallelism can well control the throughput for versatile applications. The VLSI architecture is implemented with 40 nm technology and constrained with the voltage of 1.08 V and the clock frequency of 156 MHz. The detector achieves 312 Mbit/s throughput with the powe/＂ dissipation of 23 mW and the latency of 0. 051 ns .