1TAK Y S. A 2-V 900 MHz monolithic CMOS dual- loop frequency synthesizer for GSM receivers [D]. Hong Kong.. Hong Kong University of Science and Technology, 1999.
2ROHDE U L. RF and microwave digital frequency synthesizers[M]. New York: Wiley, 1997.
3AKTAS A, ISMAIL IVll CMOS PLL calibration techniques [J]. IEEE Circ Dev Mag, 2004, 20(5): 6-11.
4WILSON W B, MOON U, LAKSHMIKUMAR K R, et al. A CMOS selbcalibrating frequency synthesizer [J]. IEEE J Sol Sta Cire, 2000, 35(10) : 1437-1444.
5HUANGSZ, LINW, GAO FL. Awide band and low PN PLL design for digital tuner [C]//IEEE Asia Pacific Conf. Macao, China. 2008: 1140-1143.
6AHN T-W, MOON J-C, MOON Y. A fractional-N frequency synthesizer with a wide-band small gain- fluctuation VCO for mobile DTV applications [C] // 7th Int Conf ASIC. Guilin, China. 2007.. 303-306.
7HUANG Z-D, KUO F-W, WANG W-C, et al. A 1. 5-V 3-10 GHz 0. 18-μm CMOS frequency synthesizer for MB-OFDM UWB applications [C] // 2008 IEEE MTT-S Int. Atlanta, GA, USA. 2008: 229-232.
8BOHN F, WANG H, NATARAJAN A S, et al. A fully integrated frequency and phase generation for a 6 -t8 GHz tunable multi-band phased-array receiver in CMOS [C] //Radio Freq Integ Circ Symp. Atlanta, GA, USA. 2008: 439-442.
9CHANG J-H, KIM C-K. A symmetrical 5-GHz fully integrated cascode coupling CMOS LC quadrature VCO [J]. IEEE Microwave Wireless Component Lett, 2005, 15: 670-672.