一种面向嵌入式系统总线的低功耗优化方法

Low Power Optimization Method Oriented to Embedded System's Bus

为了解决嵌入式系统设备总线的功耗问题,从软件方面的功耗优化入手,提出一种面向嵌入式系统总线的低功耗优化方法,即在编译阶段,分别对指令地址总线和数据总线进行优化,以减少总线的翻转次数,降低其功耗。具体方法为:针对指令地址总线,采用改进后的遗传算法进行函数段调用优化,然后结合T0编码,减少总线翻转次数,从而降低其功耗。针对指令数据总线,采用粒子群算法进行指令调度优化,然后结合0-1翻转编码,减少总线翻转次数,从而降低其功耗。为了验证上述方法的正确性和有效性,以HR6P系列微处理器为平台展开实验,实验结果表明,总线功耗的优化效率达到25%左右。该方法明显减少了总线的翻转次数,提高了系统的整体性能。

This paper put forward a method which can optimize power consumption of bus in embedded system on the base of software optimization. In the process of compiling,if instruction address bus and data bus can be optimized re- spectively to reduce the bus-invert frequency, the power consumption will be cut down. The concrete procedure is as fol- lows. For instruction address bus, using the modified genetic algorithm to optimize function call and combinating TO code, bus-invert frequency will be reduced and the power consumption will be reduced as well. For instruction data bus, using particle swarm algorithm to optimize instruction scheduling and combining 0-1 bus-invert code, bus-invert fre- quency will be reduced and the power consumption will be reduced as well. In order to verify the correctness and effec- tiveness of the method, HR6P serial microcontroller is used as an experiment platform. The experiment result shows that optimization efficiency of bus power consumption can reach about 25%. Therefore, it means the method obviously reduces bus-invert frequency and improves the whole system＇s performance.