高性能浮点除法和开方的设计与实现

Design and Implementation of High-performance Float-point Division and Square Root

在基于现场可编程门阵列(FPGA)的设计中,低延时、高吞吐量、小面积是3个主要考虑因素。针对以上因素,提出不同基数SRT浮点除法和开方算法,设计基于Virtex-II pro FPGA的可变位宽浮点除法和开方的3种实现方案,包括小面积的迭代实现、低延时的阵列实现和高吞吐量的流水实现。实验结果表明,对于浮点除法和开方算法的流水实现,在综合面积符合要求的基础上,实现频率最高分别可达到180 MHz和200 MHz以上,证明了该实现方案的有效性。

Low latency, high throughput and small area are three major design considerations of a design based on FPGA. In view of the above factors, this paper puts forward different cardinal SRT float-point division and square root algorithm. It designs three implementations of float-point division and square root operations with variable width based on Virtex-II pro FPGA. One is a low cost iterative implementation, another is a low latency array implementation, and the third is a high throughput pipelined implementation. Experimental results show that the highest frequencies for the float-point division and square root algorithm can reach above 180 MHz and 200 MHz respectively with meeting the needs of synthesized area. it fully verifies the effectiveness of the implementation plan.