期刊文献+

一种用于横向高压器件的曲率结扩展技术

A Novel Curved Junction Extension Technology for Lateral High-voltage Device
下载PDF
导出
摘要 提出一种用于横向高压器件的曲率结扩展技术,并在横向双扩散MOSFET(LDMOS)上进行了实验验证。该技术采用一个轻掺杂的p-sub层,插入LDMOS的曲率结区域,从而将高掺杂的小曲率半径p-body/n-drift突变结调整为低掺杂的大曲率半径p-sub/n-drift结,降低了p-body/n-drift突变结的电场峰值,避免了在该处发生提前的雪崩击穿。该技术已成功应用于超结LDMOS,实验结果显示,应用了该技术的超结器件击穿电压达800 V。 A novel curved junction extension technology for lateral high-voltage device is proposed and experimentally demonstrated.A low-doped p-sub,which is inserted in the curved region of the lateral diffused MOSFET(LDMOS), adjusts the high-doped abrupt p-body/n-drift junction with small curvature radius to low-doped p-sub/n-drift junction with large curvature radius,thus reducing peak electric field and avoiding premature avalanche breakdown at the curved abrupt p-body/n-drift junction.The proposed technology has been applied into a super junction LDMOS.The experimental result indicates that the super junction LDMOS with the proposed technology exhibits off-state breakdown voltage of 800 V.
出处 《电力电子技术》 CSCD 北大核心 2013年第12期8-10,共3页 Power Electronics
基金 中国博士后科学基金(2012M511327)~~
关键词 横向高压器件 曲率结扩展 曲率半径 超结 lateral high-voltage device curved junction extension curvature radius super junction
  • 相关文献

参考文献6

  • 1Mao K,Qiao M,Jiang L L,et al.A 0.35 Ixm 700 V BCD Technology With Self-isolated and Non-isolated Ultra-low Specific On-resistance DB-nLDMOS[A].The International Symposium on Power Semiconductor Devices and ICs[C]. Kanazawa, Japan, 2013 : 397-400.
  • 2Kim S, Kim J, Prosack H.Novel Lateral 700 V DMOS for Integration : Ultra-low 85 m em2 On-resistance, 750 V LFCC[A].The International Symposium on Power Semicon- ductor Devices and ICs [C].Brnges, Belgium, 2012 : 185 - 188.
  • 3Qiao M, Hu X ,Wen H J, et al.A Novel Substrate-assisted RESURF Technology for Small Curvature Radius June- tion[A].The International Symposium on Power Semicon- ductor Devices and ICs[C].San Diego, USA, 2011 : 16-19.
  • 4Basavanagoud C, Bhat K N.Effect of Lateral Curvature on the Breakdown Voltage of Planar Diodes[J].IEEE Elec- tron Device Lett., 1985,6(6) : 276-278.
  • 5Shibib M A.Area-efficient Layout for High Voltage Lat- eral devices : US, 5534721 [P]. 1996.
  • 6Lee S H,Jeon C K,Moon J W,et al.700 V Lateral DMOS With New Source Fingertip Design[A].The International Symposium on Power Semiconductor Devices and ICs[C]. Oralando, FL, 2008 : 141-144.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部