ESD performance of LDMOS with source-bulk layout structure optimization

ESD performance of LDMOS with source-bulk layout structure optimization

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摘要 To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vtl is reduced from 55.53 to 50.69 V. To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vtl is reduced from 55.53 to 50.69 V.

作者蒋苓利樊航林丽娟张波

机构地区 State Key Laboratory of Electronic Thin Film and Integrated Devices

出处《Journal of Semiconductors》 EI CAS CSCD 2013年第12期40-44,共5页 半导体学报（英文版）

基金 Project supported by the National Natural Science Foundation of China(Nos.60906038,61076082)

关键词 ESD LDMOS source-bulk layout structure ESD LDMOS source-bulk layout structure

分类号 TN386 [电子电信—物理电子学]

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参考文献13

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Journal of Semiconductors

2013年第12期

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ESD performance of LDMOS with source-bulk layout structure optimization

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