逆向二进制防碰撞算法及其FPGA硬件实现

Converse Binary Anti-collision Algorithm and Hardware Implementation Based on FPGA

针对常用几种二进制防碰撞算法阅读器和电子标识之间交互次数较多、通讯数据量较大的缺点,提出一种便于硬件实现的逆向二进制防碰撞算法。新算法从叶子结点开始逆向构建识别树,在最底两层完成标识识别。模拟仿真和理论分析均验证了新算法的实用性和高效性。同时提出新算法基于FPGA的硬件实现方案。与其他方法的硬件方案相比,该算法方案硬件加速比可达4,数据通信量可达12M B/s。模拟仿真表明硬件实现方案结构简单,资源耗费少,识别周期短,通信速率高,具有更高的硬件加速比,为算法的实际应用提供了良好基础。

According to the general binary algorithm＇s disadvantage of requiring more interactive times and more communication data,a new algorithm easy for hardware implementation was proposed. In the algorithm,the identification tree was constructed from leaves and the tags were identified on the lowest two levels. The algorithm is proved to be practical and effective by simulation and theoretical analysis. The according hardware implementation schema were also given. Compared with other algorithms＇ ,the schema＇s hardware acceleration ratio is up to 4,and the communication data is 12 MB/s. Testing results showed that the schema of hardware implementation was simpler, shorter identification period, higher communication ratio and hardware speedup ratio. Its application in practical engineering can be greatly promoted.