基于CPLD的光电编码器快速运算电路设计

Design of photoelectric encoder operational circuit based on CPLD

主要运用Quartus 5.1软件开发平台,利用VHDL语言编程和仿真,基于Altera公司MAXⅡ系列CPLD芯片EPM1270T144C5实现了硬件六十进制压缩BCD码加减运算功能。将设计的CPLD电路应用到光电编码器电路中,实现光电编码器的快速运算,提升了位置检测系统的动态性能指标。详细介绍了电路的原理、设计思路和软件设计,分析了目前设计中的不足之处,提出了部分改进建议。

The paper introduces a photoelectric encoder circuit for performing sixty arithmetical operation of compressed BCD codes. Using VHDL in programming and simulation, the software is developed on the platform of Quartus 5.1, and the hardware is based on EPM1270TI44C5 which is a CPLD of the Altera＇s MAX 11 family. The acquired encoder circuit can make the photoelectric encoder do faster arithmetical operation to advance the dynamic performance level of a position detecting system. The paper introduces the principle and design of the encoder circuit and successfully make it work in the system. It also finds out several defects in the current system and proposes some suggestions to make an improvement.