两级同步:面向众核处理器的并行仿真机制

Two-Level Synchronization: A Parallel Simulation Mechanism for Many-Core Architecture

针对并行仿真众核处理器计算机过程中同步对仿真器性能、精度的制约问题,提出一种两级同步机制,第一级同步作用于众核处理器片上所有节点间,维持逻辑时间的全局一致性;第二级同步作用于每颗节点内的一级或二级高速缓存与片上网络路由器间,在提升并行性的同时保证处理器内各组件的高精度建模。理论分析给出了两级同步性能的上下界。实验结果表明两级同步具有较好的加速比及合理的可扩展性。

To address performance and accuracy problems caused by synchronization as simulating a many-core computer in parallel, two-level synchronous mechanism is proposed. The first level synchronization functioning among all nodes ensures the global time order. The second level synchronization maintains the time order between high level caches and the NoC （Network on Chip） router on one node, which improves parallelism without hurting fidelity of models. The theoretical analysis reveals the upper and lower bounds on the performance of proposed mechanism. And the experiment shows it obtains good speed-up and reasonable scalability.